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| Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
| arm:cm [2023/06/21 09:10] – niziak | arm:cm [2023/07/24 21:17] (current) – niziak | ||
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| Line 7: | Line 7: | ||
| to PC (without bit zero) so PC value is even and bit 0 is copied into xPSR '' | to PC (without bit zero) so PC value is even and bit 0 is copied into xPSR '' | ||
| + | |||
| + | ===== hardfault with PC: 0xfffffffd ===== | ||
| + | |||
| + | LR = 0xFFFFFFFD means that the return stack is the PSP (not the MSP). | ||
| ===== hardfault with PC: 0xfffffffe ===== | ===== hardfault with PC: 0xfffffffe ===== | ||
| Cortex M has only 31:1 bits in PC register (even addresses only). | Cortex M has only 31:1 bits in PC register (even addresses only). | ||
| - | This address is a special | + | This address is a special |
| Probably during handling fault another fault occurs. | Probably during handling fault another fault occurs. | ||