http://192.168.180.206:8001/ 2026-05-13T01:19:27+00:00 http://192.168.180.206:8001/ http://192.168.180.206:8001/_media/wiki:dokuwiki.svg text/html 2023-07-24T19:17:57+00:00 Anonymous (anonymous@undisclosed.example.com) http://192.168.180.206:8001/arm:cm?rev=1690226277&do=diff Cortex-M Cortex-M doesn't support ARM instruction set. It only supports “Thumb” instruction set. Bit 0 from PC is copied to T bit in xPSR. It instructs CPU about next instruction mode (0-ARM mode, 1-thumb mode). If T bit is zero, Usage fault exception is raised. text/html 2024-06-05T13:43:02+00:00 Anonymous (anonymous@undisclosed.example.com) http://192.168.180.206:8001/arm:exclusive_monitor?rev=1717594982&do=diff Exclusive Monitor The Cortex-M4 processor implements a local exclusive monitor. For more information about semaphores and the local exclusive monitor see the ARMv7M ARM Architecture Reference Manual. Instructions: * LDREX - Load-Exclusive * STREX - Store-Exclusive * CLREX - Clear-Exclusive text/html 2025-11-16T12:19:29+00:00 Anonymous (anonymous@undisclosed.example.com) http://192.168.180.206:8001/arm:neon?rev=1763295569&do=diff Neon Bayer RAW10 packed to Y16 Data is organised in 5 bytes packed chunks to store 4 x RAW10 pixel data: General idea: * Load data * Neon can perform interleaved loads by 4 * Neon can use lookup table load, so we can specify what byte loads where text/html 2024-07-29T19:10:15+00:00 Anonymous (anonymous@undisclosed.example.com) http://192.168.180.206:8001/arm:pm?rev=1722280215&do=diff Power Management <https://devzone.nordicsemi.com/f/nordic-q-a/10424/nrf51422-won-t-sleep#post-id-58214> WFE Wait For Event It is only hint and depends on implementation. The WFE instruction allows (but does not require) the processor to enter a low-power state until some event occurs such as a SEV being issued by another processor.